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IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Truth Table I—Read/Write and Enable Control
Industrial and Commercial Temperature Ranges
(1,2,3,4,5)
OE
X
X
X
CLK
CE 0
H
X
L
CE 1
X
L
H
Byte Enables
All BE = X
All BE = X
All BE = H
R/ W
X
X
X
ZZ
L
L
L
I/O Operation (6)
All Bytes= High-Z
All Bytes = High-Z
All Bytes = High-Z
MODE
Deselected: Power Down
Deselected: Power Down
All Bytes Deselected
X
L
H
BE n = L, All other BE = H
L
L
Byte n = D IN , All other Bytes = High-Z Write to Byte X Only
X
X
X
L
L
L
H
H
H
BE 4-7 = L, BE 0-3 = H
BE 4-7 = H, BE 0-3 = L
BE 0-7 = L
L
L
L
L
L
L
Byte 4-7 = D IN , Byte 0-3 = High-Z
Byte 4-7 = High-Z, Byte 0-3 = D IN
Byte 0-7 = D IN
Write to Lower Bytes Only
Write to Upper Bytes Only
Write to All Bytes
L
L
H
BE n = L, All other BE = H
H
L
Byte n = D OUT , All other Bytes = High-Z Read Byte X Only
L
L
L
L
L
L
H
H
H
BE 4-7 = L, BE 0-3 = H
BE 4-7 = H, BE 0-3 = L
All BE = L
H
H
H
L
L
L
Byte 4-7 = D OUT , Byte 0-3 = High-Z
Byte 4-7 = High-Z, Byte 0-3 = D OUT
All Bytes = D OUT
Read Lower Bytes Only
Read Upper Bytes Only
Read All Bytes
H
X
X
X
X
X
X
X
All BE = X
All BE = X
X
X
L
H
All Bytes = High-Z
All Bytes = High-Z
Outputs Disabled
Sleep Mode
5687 tbl 03
NOTES:
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. ADS , CNTEN , REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5. For the examples shown here, BE n may correspond to any of the eight byte enable signals.
Truth Table II—Address Counter Control
(1,2)
Previous
Internal
Address
An
Internal
Address
X
Address
Used
An
CLK
ADS (4)
L
CNTEN
X
REPEAT (4,6)
H
I/O (3)
D I/O (n)
External Address Used
MODE
L
X
X
An
An + 1
An + 1
An + 1
H
H
(5)
H
H
H
D I/O (n+1) Counter Enabled-Internal Address generation
D I/O (n+1) Enabled Address Blocked-Counter disabled (An + 1 reused)
X
X
An
X
X
L
D I/O (n)
Counter Set to last valid ADS load
NOTES:
5687 tbl 04
1. "H" = V IH, "L" = V IL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/ W , CE 0 , CE 1 , BE n and OE .
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE 0 , CE 1 and BE n.
5. The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE 0 , CE 1 , BE n.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS . This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
5
6.42
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